Loading…
Loading…
I also heard something about thinking that at full scale, gate-all-around could be something like 300,000 wafer per month
what's your view on pacing here and whether this could cause these investments perhaps to spread out over a longer horizon
I think you previously disclosed that $549 million reduction in backlog for the fiscal year in a filing
How much of your continued optimism on market and KLA growth in packaging next year involves expansion opportunities in HBM packaging?
how much of that second half outlook is tied to new cleanroom space availability
your near-term opportunity set in advanced packaging was particularly in 2.5D or CoWoS packaging rather than in HBM. Is that the case?
can you comment on the magnitude of residual spending you still see with them besides R&D and technology development?
how about the process control intensity going from 2 nanometer [indiscernible] around to 16A?
Of the $8 billion in WFE spending, on a kind of rough cut, could you partition that across on a percentage basis, advanced logic, DRAM and NAND?
is that for a 400-layer application?
For trying to resist deposition in development, can you remind us of the SAM or maybe revenue potential